1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor device.
2. Description of the Related Art
In general, a protection circuit for preventing an electrical over-stress (EOS) is provided in a semiconductor device. The EOS is an electrical shock such as abnormal over-current or over-voltage due to leakage current and voltage of plants using a power supply voltage, and may occur for nanoseconds to milliseconds. When the EOS occurs, a gate oxide layer of a transistor included in an internal circuit may be broken. Thus, the protection circuit is essentially provided to protect the internal circuit from the EOS.
FIG. 1 is a block diagram illustrating a conventional protection circuit. FIG. 2 is a detailed circuit diagram illustrating an over-voltage discharge unit shown in FIG. 1.
Referring to FIG. 1, the protection circuit 10 includes an external voltage detection unit 11 and an over-voltage discharge unit 13. The external voltage detection unit 11 detects a voltage level of a supply voltage VDD supplied from external, to output an external voltage detection signal HVDD. The over-voltage discharge unit 13 discharges the supply voltage VDD in an over-voltage state in response to the external voltage detection signal HVDD.
Here, the external voltage detection unit 11 continuously detects the voltage level of the supply voltage VDD and activates the external voltage detection signal HVDD when the supply voltage VDD is out of range to be in the over-voltage state. The over-voltage discharge unit 13 returns the supply voltage VDD to a normal-voltage state from an over-voltage state by a discharging operation when the external voltage detection signal HVDD is activated.
As shown in FIG. 2, the over-voltage discharge unit 13 includes a first inverter INV1, a second inverter INV2, and an NMOS transistor N1. The first inverter INV1 inverts the external voltage detection signal HVDD. The second inverter INV2 inverts an output of the first inverter INV1. The NMOS transistor N1 has a drain-source path between a supply voltage (VDD) terminal and a ground voltage (VSS) terminal and a gate coupled to the ground voltage (VSS) terminal, and receives an output signal of the second inverter INV2 as a bulk bias. Accordingly, when the supply voltage VDD is in an over-voltage state due to an EOS the over-voltage discharge unit 13 may perform a discharge operation by forming a discharge path D from a PMOS transistor P1 included in the second inverter INV2 to a source terminal of the NMOS transistor N1, in response to the external voltage detection signal HVDD.
Meanwhile, a semiconductor device includes plural internal voltage generation circuits for generating various internal voltages required for an internal operation based on the supply voltage VDD supplied from external. The internal voltage generation circuits may be classified with a pump type and a regular type. In a case of the pump type, the internal voltage generation circuits generate a voltage whose level is higher than the supply voltage VDD, e.g., a boost voltage VPP, and a voltage whose level is lower than the ground voltage VSS, e.g., a back-bias voltage VBB, through a charge pumping method. In a case of the regular type, the internal voltage generation circuits generate a positive voltage that is used in the semiconductor device and has a level lower than the supply voltage VDD, e.g., a core voltage VCORE, a bit line precharge voltage VBLP, or the like, through a voltage down-converting method.
FIG. 3 is a block diagram illustrating a conventional internal voltage generation circuit. FIG. 4 is a detailed circuit diagram illustrating the conventional internal voltage generation circuit shown in FIG. 3.
Referring to FIG. 3, the internal voltage generation circuit 20 includes a reference voltage generation unit 21 and an internal voltage generation unit 23. The reference voltage generation unit 21 generates a reference voltage VREF based on the supply voltage VDD. The internal voltage generation unit 23 is a pump type to generate a boost voltage VPP corresponding to the reference voltage VREF.
Here, the reference voltage generation unit 21 generates the reference voltage VREF corresponding to a target level of the boost voltage VPP using the supply voltage VDD.
Referring to FIG. 4, the internal voltage generation unit 23 includes an internal voltage detector 23A, an oscillator 23B, and a pump 23C. The internal voltage detector 23A compares the boost voltage VPP with the reference voltage VREF to generate a pumping enable signal EN. The oscillator 23B outputs an oscillation signal OSC in response to the pumping enable signal EN. The pump 23C generates the boost voltage VPP in response to the oscillation signal OSC. Here, the internal voltage detector 23A activates the pumping enable signal EN when the boost voltage VPP is lower than the reference voltage VREF, and deactivates the pumping enable signal EN when the boost voltage VPP is higher than or identical to the reference voltage VREF. The pump 23C generates the boost voltage VPP by boosting the supply voltage VDD in response to the oscillation signal OSC.
However, the above semiconductor device may have following concerns.
FIG. 5 is a graph illustrating an abnormal operation of a conventional semiconductor device.
Hereinafter, referring to FIGS. 1 to 5, an operation of the semiconductor device is described in detail.
When the supply voltage VDD is in an over-voltage state under the influence of the EOS, the protection circuit 10 of FIG. 1 is enabled to lower the supply voltage VDD to a normal-voltage state. At this time, during a period from the over-voltage state to the normal-voltage state, the internal voltage generation circuit 20 of FIG. 3 malfunctions due to the supply voltage VDD in the over-voltage state.
For example, if the reference voltage VREF is increased due to the supply voltage VDD in the over-voltage state, the internal voltage generation unit 23 may perform an abnormal pumping operation, and thus the internal voltage generation unit 23 increases the boost voltage VPP until a target level corresponding to the supply voltage VDD in the over-voltage state.
As shown in FIG. 5, when the supply voltage VDD is in an over-voltage state (refer to a solid line) under the influence of the EOS, the boost voltage VPP becomes in an abnormal state (refer to a solid line). Then, when the supply voltage VDD returns to a normal-voltage state (refer to a dotted line) by the protection circuit, the boost voltage VPP also becomes in a normal state (refer to a dotted line). At this time, even if the supply voltage VDD returns to the normal-voltage state from the over-voltage state, the reference voltage VREF may not return to a normal state within a desirable time but stays in an abnormal state. That is, there may be the time difference between the supply voltage VDD and the reference voltage VREF in order to return to the normal state, and the time difference is determined by a performance of the reference voltage generation unit 21.
Therefore, due to the abnormal pumping operation of the internal voltage generation unit 23, the supply voltage VDD is excessively consumed. Accordingly, power lines near the internal voltage generation unit 23, i.e., power lines for supplying the supply voltage VDD, may be deteriorated.